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ICs for TV
AN2546FH-A
Automotive LCD TV signal processor IC
Overview
The AN2546FH-A is a video signal processing IC built-in a 5-volt power-supply source driver for TFT color LCD (normally white type), and it supports the NTSC, PAL and PAL-M/PAL-N systems. The main circuitry of this IC includes video-signal processing circuit, color signal processing circuit, interface circuit, synchronizing circuit and many color quality adjusting circuits. This IC converts the composite video signal or separated Y/C signal or RGB signals into RGB signals available for TFT color LCD.
12.000.20 10.000.20 48 49 33 32
Unit: mm
64 1 0.50 16
17
(1.25)
Features
* Supply voltage: 3 V/5 V/7.5 V * Built-in a 5-volt power-supply source driver for TFT type LCD * Low consumption power (typ. 200 mW) * Supporting the NTSC, PAL, PAL-M and PAL-N systems * Supporting composite, component and color differential signal input * Video signal, analog RGB (2 systems) One is for OSD (analog/digital). * Each mode setting is possible with I2C Bus control. * Electronic volume (D/A converter) built in * Contrast/Brightness/ correction circuit built in * Horizontal and vertical display position adjustment are possible by serial control. * Improvement of weak electric field characteristics (Compared to AN2526FH/AN2526NFH: -5 dB) * At reverse stop, built-in output gain down function
0.100.10
+0.10
0.18-0.05
+0.1
0.15-0.05 1.950.20
(1.25) 10.000.20 12.000.20
(1.00)
Seating plane
0 to 10 0.500.20
QFP064-P-1010 Note) The package of this product will be changed to lead-free type (QFP064-P-1010A). See the new package dimensions section later of this datasheet.
Applications
* 4 inches to 7 inches middle size TFT LCD equipment of normally white, of such as an in-car TV and an LCD monitor for car navigation system.
Publication date: February 2003
SDB00081BEB
1
2
L-det. Sync. in 0.47 F NAVI VCC1 sync. (5.0 V) VDD NRGB POL C-sync. VSS 82 k SCP 15 F AFC 10 k 3.3 k det. 0.022 F GND2 1 M 0.02 F 50 k 100 k 680 pF VCC3
68 k
AN2546FH-A
VCC1
330
SDATA SCLCK
15 k
4.7 F
1 500 pF
48
Reg. I2C Bus Sync. sepa. VCO 1/n Logic Logic Logic
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1. Composite signal input
Composite signal
PONR
49
Logic
32 31
10 F 33 k HHKILL VSYNC drop Phase comp. f det.
2.2 F 50 COM DC
HD VD PWM 30 29 PWM VCC3 (3.0 V)
DAC
Application Circuit Examples
SECAM black level adj. Clamp SW Vert. count Delay Invert Sharpness ACC amp. R-Y, B-Y DEMOD GCA Gamma Limit Sync. cut
51
DAC
330 k 1 k
52
47 H
4.7 F
Y-in
53
VCOM 28 27
VCOM R-out det. 2.2 F 26 R-out 25 24 VCC2 (7.5 V) 23
2 k
NTSC = 39 pF 0.1 F PAL = 27 pF 55 Y-det.
54
ACC det. BPF
56
SDB00081BEB
Bright APC YUV SW GCA Killer Reg. Int./Ext. SW G-Y gene. VXO gene. VXO Tint Matrix OSD SW
C-in
0.1 F
ACC det.
57
VCC1 (5.0 V)
58
Contrast
0.01 F GND1 22 G-out det. 2.2 F 21 G-out 20
59 GND3 0.1 F 60 Kill det. 0.02 F 61 APC det.
62
B-out det. 2.2 F 19 B-out 18 Clamp. 17 BLAK YS
63
1 F 5.1 k Recommended crystal oscillator SC out NTSC: VSX0160 NTSC (KINSEKI, Limited) PAL: VSX0162 PAL or (KINSEKI, Limited) PAL-M
64
10
11
12
13
14
15
16
1
2
3
4
5
6
15 F
7
8
9
Be sure to attach a power supply filter to a power supply pin. 47 H
1 F VCC1 (5.0 V) V REF R-in1 B-Y in G-in1 B-in1
1 F
1 F
Power supply pin R-Y out B-Y out R-Y in
15 F
PAL-N
R-in2 G-in2 B-in2 R-det. G-det. B-det. * C coupling input in an analog OSD mode. * Connect to GND in case of no use in a digital OSD mode.
L-det. Sync. in 0.47 F NAVI VCC1 sync. (5.0 V) VDD NRGB POL C-sync.
35 34 33 39 38 37 36
VCC3 50 k 100 k 82 k SCP 680 pF
68 k VSS
VCC1 AFC 10 k 3.3 k det. 15 F
41 40 48 47 46 45 44 43 42
330
SDATA SCLCK
0.022 F GND2 1 M
0.02 F
15 k Brightness and syncronous signal Reg. I2C Bus Sync. sepa. VCO 1/n Logic Logic Logic 32 31 PWM 30 29 VCOM 28 27 Invert Sharpness ACC amp. R-Y, B-Y DEMOD GCA Gamma Limit
4.7 F
1 500 pF
2. Component signal input
PONR
49
10 F 33 k HHKILL VSYNC drop Phase comp. f det.
2.2 F 50 COM DC
Logic
HD VD PWM VCC3 (3.0 V) VCOM
DAC
SECAM black level adj. Clamp SW Vert. count Delay Sync. cut
51
DAC
330 k 1 k
52
4.7 F
Y-in
53
Application Circuit Examples (continued)
54
0.1 F
Y-det.
55
R-out det. 2.2 F 26 R-out 25 24 VCC2 (7.5 V) 23
ACC det. BPF
56
0.1 F
ACC det.
SDB00081BEB
Bright APC YUV SW GCA Killer Reg.
1 2 3 4 5 6 7 8
C-in
57
VCC1 (5.0 V)
58
Contrast
0.01 F GND1 22 G-out det. 21 2.2 F G-out 20
59 GND3 0.1 F 60 Kill det. 0.02 F 61 APC det. Tint G-Y gene. VXO gene. VXO
1 F 5.1 k SC out
62
Matrix
OSD SW
B-out det. 19 2.2 F B-out 18 Int./Ext. SW
10 11 9
63
BLAK Clamp.
12 13 14 15 16
Recommended crystal oscillator NTSC: VSX0160 NTSC (KINSEKI, Limited) PAL: VSX0162 PAL or (KINSEKI, Limited) PAL-M 15 F VCC1 (5.0 V) V REF B-Y in
64
17
YS 1 F R-in1 G-in1 B-in1 1 F 1 F
Be sure to attach a power supply filter to a power supply pin. 47 H
Power supply pin R-Y out B-Y out R-Y in
AN2546FH-A
15 F
PAL-N
R-in2 G-in2 B-in2 R-det. G-det. B-det. * C coupling input in an analog OSD mode. * Connect to GND in case of no use in a digital OSD mode.
3
4
VCC1 510 k 510 k L-det. 50 k 100 k 82 k POL C-sync. SCP GND2 NRGB 15 F VDD VSS 1 M 0.02 F 680 pF VCC3 Required only when not using crystal oscillators. 0.022 F Sync. in 0.47 F NAVI VCC1 sync. (5.0 V) AFC 10 k 3.3 k det.
AN2546FH-A
68 k
VCC1
330
SDATA SCLCK
3. Analog RGB signal input
15 k
4.7 F
1 500 pF
48
Reg. I2C Bus Sync. sepa. VCO 1/n Logic Logic
47
46
45
44
43
42
41
40
39
38
37
36
35
34
Synchronous signal
PONR
49
Logic
Logic
33
32 31 PWM 30 29 VCOM 28 27 HD VD PWM VCC3 (3.0 V) VCOM
10 F 33 k HHKILL VSYNC drop Phase comp. f det.
2.2 F 50 COM DC
DAC
SECAM black level adj. Clamp SW Vert. count Delay Invert Sharpness ACC amp. R-Y, B-Y DEMOD GCA Gamma Limit Sync. cut
51
DAC
330 k 1 k
52
Application Circuit Examples (continued)
53
Possible to change the synchronous signal input pin according to the channnel 10 value. Possible to input to pin 45 by 3 V[p-p] positive polarity pulse.
54
55
R-out det. 2.2 F 26 R-out 25 24 Contrast 23 22 Bright 0.01 F GND1 VCC2 (7.5 V)
SDB00081BEB BPF APC YUV SW GCA Killer Reg. Int./Ext. SW Clamp. VXO gene. VXO Tint G-Y gene. Matrix OSD SW
56
ACC det.
57
VCC1 (5.0 V)
58
GND3
59
60
G-out det. 2.2 F 21 G-out 20
61
Recommended crystal oscillator NTSC: VSX0160 (KINSEKI, Limited) PAL: VSX0162 (KINSEKI, Limited)
62
B-out det. 2.2 F 19 B-out 18 17 BLAK YS
NTSC
63
Apply a half VCC1 voltage to pin 42 according to resistance division when not connecting crystal oscillators.
PAL or PAL-M
64
10
11
12
13
14
15
16
1
2
3
4
5
6
Be sure to attach a power supply filter to a power supply pin. 47 H
15 F 4.7 F 4.7 F 4.7 F VCC1 (5.0 V) V REF R-in1 G-in1 B-in1
7
8
9
1 F
1 F
1 F
Power supply pin
15 F
PAL-N
R-in2 G-in2 B-in2 R-det. G-det. B-det. * C coupling input in an analog OSD mode. * Connect to GND in case of no use in a digital OSD mode.
AN2546FH-A
Pin Descriptions
Pin No. 1 2 3 4 5 6 Description Crystal oscillator connecting pin 3 (PAL-N) R-Y output pin B-Y output pin R-Y input pin B-Y input pin Signal processing system power supply (VCC1 = 5.0 V) 7 Internal reference power supply detection pin (2.0 V) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 R-ch. analog signal input pin G-ch. analog signal input pin B-ch. analog signal input pin R-ch. clamp detection pin G-ch. clamp detection pin B-ch. clamp detection pin R-ch. OSD input pin G-ch. OSD input pin B-ch. OSD input pin Character picking up pulse input pin Side black control signal input pin B-ch. output pin B-ch. output DC feedback detection pin G-ch. output pin G-ch. output DC feedback detection pin GND 1 Drive output reference voltage input pin Drive system power supply (VCC2 = 7.5 V) R-ch. output pin R-ch. output DC feedback detection pin Common reverse signal output pin Pulse output system power supply (VCC3 = 3.0 V) 30 31 32 PWM output pin Vertical synchronous signal output pin Horizontal synchronous signal output pin 59 60 61 62 63 64 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 Description Sand castle pulse output pin Composite synchronous signal output pin Vertical synchronous signal input pin 1H reverse signal input pin Clock-system GND (VSS) Analog imposing control signal input pin Horizontal clock detection pin Clock-system power supply (3.0 V) GND 2 AFC loop filter connecting pin VCO frequency adjustment pin Synchronous system power supply (VCC1 = 5.0 V) NAVI signal synchronous signal input pin Synchronous signal input pin Serial data shift clock input pin Serial data input pin Power-on reset detection pin Common DC adjustment voltage output pin DAC output pin Luminance signal input pin Chrominance signal trap filter connection pin 1 Chrominance signal trap filter connection pin 2 Y-system clamp detection pin ACC detection pin Chrominance signal input pin Chrominance processing system power supply (VCC1 = 5.0 V) GND 3 Chrominance killer detection pin APC detection pin Subcarrier output pin Crystal oscillator connecting pin 1 (NTSC) Crystal oscillator connecting pin 2 (PAL/PAL-M)
SDB00081BEB
5
AN2546FH-A
Absolute Maximum Ratings
Parameter Supply voltage Symbol VCC1 VCC2 VCC3 Supply current Power dissipation
*2 *1
Rating 5.5 8.5 5.2 423 -30 to +85 -55 to +150
Unit V
ICC PD Topr Tstg
*1
mA mW C C
Operating ambient temperature Storage temperature
Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25C. *2: The power dissipation shown is the value in free air for Topr = 85C.
Recommended Operating Range
Parameter Supply voltage Symbol VCC1 VCC2 VCC3 Range 4.7 to 5.3 7.0 to 8.0 2.7 to 3.3 Unit V
Electrical Characteristics at Ta = 25C
Parameter DC VCC1-system current consumption VCC2-system current consumption VCC3-system current consumption Chrominance system R-Y standard gain R-Y/G-Y relative gain B-Y standard gain B-Y/G-Y relative gain High-level APC pull-in Low-level APC pull-in ACC output characteristic 1 ACC output characteristic 2 Chrominance killer characteristic 1 Chrominance killer characteristic 2 Subcarrier amplitude Y-system Sharpness control characteristic Sharpness frequency characteristic 1 R-ch. contrast adjustment range 1 6 GSH fSH1 CTRR1 Refer to product standards Refer to product standards Refer to product standards
SDB00081BEB
Symbol
Conditions
Min
Typ
Max
Unit
ITOTAL1 ITOTAL2 ITOTAL3
Refer to product standards Refer to product standards Refer to product standards
32 1.0
44 9.0 2.0
mA mA mA
GRY GRYGY GBY GBYGY APH APL GACC1 GACC2 VKILL1 VKILL2 SCV
Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards
9.0 -5.0 9.0 -15 500 -540 -1.0 -1.0 400 400
15 -1.0 15 -9.0 540 -500 1.0 1.0
dB dB dB dB Hz Hz dB dB mV[p-p]
600 mV[p-p] mV[p-p]
1.0 4.0 1.5
dB dB dB
AN2546FH-A
Electrical Characteristics at Ta = 25C (continued)
Parameter Y-system (continued) G-ch. contrast adjustment range 1 B-ch. contrast adjustment range 1 R-ch. contrast adjustment range 2 G-ch. contrast adjustment range 2 B-ch. contrast adjustment range 2 R-ch. pedestal amplitude minimum CTRG1 CTRB1 CTRR2 CTRG2 CTRB2 VPEDRmin VPEDBmin Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards
SDB00081BEB
Symbol
Conditions
Min
Typ
Max -2.5 -2.5 -2.5 2.0 2.0 2.0 2.85 -3.0 -3.0 -3.0 0 0 0 3.0 3.0 3.0 2.7 2.7 2.7
Unit
1.5 1.5 3.0 3.0 3.0 2.35 -9.0 -9.0 -9.0 -8.0 -8.0 -8.0 -5.0 -5.0 -5.0 3.2 3.2 3.2 3.0 3.0 3.0 0.8 0.8 0.8
dB dB dB dB dB V[p-p] V[p-p] V[p-p] V[p-p] V[p-p] V[p-p] V[p-p] dB dB dB dB dB dB dB dB dB V[p-p] V[p-p] V[p-p] V[p-p] V[p-p] V[p-p] V V V V V V V[p-p] V[p-p] V[p-p] 7
G-ch. pedestal amplitude minimum VPEDGmin B-ch. pedestal amplitude minimum
R-ch. pedestal amplitude maximum VPEDRmax G-ch. pedestal amplitude maximum VPEDGmax B-ch. pedestal amplitude maximum VPEDBmax G-ch. output DC voltage R-ch. gamma characteristic 1 G-ch. gamma characteristic 1 B-ch. gamma characteristic 1 R-ch. gamma characteristic 2 G-ch. gamma characteristic 2 B-ch. gamma characteristic 2 R-ch. gamma characteristic 3 G-ch. gamma characteristic 3 B-ch. gamma characteristic 3 R-ch. white limiter high-level G-ch. white limiter high-level B-ch. white limiter high-level R-ch. white limiter low-level G-ch. white limiter low-level B-ch. white limiter low-level R-ch. black limiter low-level G-ch. black limiter low-level B-ch. black limiter low-level R-ch. black limiter high-level G-ch. black limiter high-level B-ch. black limiter high-level R-ch. YS threshold 1 G-ch. YS threshold 1 B-ch. YS threshold 1 VGDC GGAMR1 GGAMG1 GGAMB1 GGAMR2 GGAMG2 GGAMB2 GGAMR3 GGAMG3 GGAMB3 VWRRH VWRGH VWRBH VWRRL VWRGL VWRBL VBRRL VBRGL VBRBL VBRRH VBRGH VBRBH VtYSR1 VtYSG1 VtYSB1
AN2546FH-A
Electrical Characteristics at Ta = 25C (continued)
Parameter Y-system (continued) R-ch. YS threshold 2 G-ch. YS threshold 2 B-ch. YS threshold 2 R-ch. black level G-ch. black level B-ch. black level R-ch. black level width G-ch. black level width B-ch. black level width R-ch. CHR threshold 1 G-ch. CHR threshold 1 B-ch. CHR threshold 1 R-ch. CHR threshold 2 G-ch. CHR threshold 2 B-ch. CHR threshold 2 R-ch. white level G-ch. white level B-ch. white level R-ch. white level width G-ch. white level width B-ch. white level width R-ch. RGB2 relative amplitude B-ch. RGB2 relative amplitude Synchronous system Horizontal sync. pulse low-level Horizontal sync. pulse amplitude Horizontal sync. pulse width Vertical sync. pulse low-level Vertical sync. pulse amplitude Horizontal sync. separation pulse high-level Horizontal sync. separation pulse amplitude Horizontal sync. separation pulse width VHDL VHD tHD VVDL VVD VHSSH VHSS tHSS Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards SG2 (NTSC) SG2 (NTSC) SG2 (NTSC) 2.4 3.6 2.4 2.4 2.4 3.6 0.4 6.0 0.4 6.0 V V[p-p] s V V[p-p] V V[p-p] s VtYSR2 VtYSG2 VtYSB2 CHRRB CHRGB CHRBB WCHRRB WCHRGB WCHRBB VtCHR1 VtCHG1 VtCHB1 VtCHR2 VtCHG2 VtCHB2 CHRRW CHRGW CHRBW WCHRRW WCHRGW WCHRBW VRGB2R VRGB2B Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards Refer to product standards -1.0 -1.0 -1.0 2.0 2.0 2.0 1.5 1.5 1.5 3.0 3.0 3.0 2.0 2.0 2.0 2.0 2.0 2.0 - 0.45 - 0.45 0.5 0.5 0.5 1.0 1.0 1.0 4.0 4.0 4.0 4.0 4.0 4.0 0.45 0.45 V[p-p] V[p-p] V[p-p] V V V s s s V[p-p] V[p-p] V[p-p] V[p-p] V[p-p] V[p-p] V[p-p] V[p-p] V[p-p] s s s V[p-p] V[p-p] Symbol Conditions Min Typ Max Unit
8
SDB00081BEB
AN2546FH-A
Terminal Equivalent Circuits
Pin No. 1 Equivalent circuit Description VXO3: PAL-N crystal oscillator connecting pin Use the capacitor with temperature characteristics (N750) to connect to the crystal oscillator. Voltage * Waveform
Pin 58 VCC1 190 1 k Pin 59 GND
1
2
Pin 58 VCC1
2 k
R-Y out: Output pin of R-Y signal demodulated from video signal
R-Y signal
2 Pin 59 GND 3 Pin 58 VCC1 B-Y out: Output pin of B-Y signal demodulated from video signal
1H
B-Y signal
2 k
3 Pin 59 GND 4
1H
5 k
5 k
Pin 58 VCC1
R-Y in: R-Y signal input pin in a color difference mode and in the standard PAL
R-Y signal
2 k 4 5 k Pin 7 VREF 5 k 5 k
17.5 k
1H
Pin 59 GND
SDB00081BEB
9
AN2546FH-A
Terminal Equivalent Circuits (continued)
Pin No. 5 Equivalent circuit Description Voltage * Waveform B-Y signal B-Y in: B-Y signal input pin in a color difference mode and in the standard PAL
5 k
5 k
Pin 58 VCC1
2 k 5 5 k Pin 7 VREF 5 k 5 k
6
17.5 k
1H
Pin 59 GND
VCC1: Drive block 5.0 V-system power supply pin
7
60
Pin 6 VCC1
VREF: Reference voltage output pin 2.0 V typ.
7
1 k
200 30 k
26 k Pin 23 GND
8
Pin 6 VCC1
R-in 1: Analog R signal input
Analog R signal
0.7 V[p-p] typ.
8
5 k
Pin 7 VREF
9
Pin 23 GND Pin 6 VCC1
G-in 1: Analog G signal input Analog G signal
0.7 V[p-p] typ.
9
5 k
Pin 7 VREF
Pin 23 GND
10
SDB00081BEB
AN2546FH-A
Terminal Equivalent Circuits (continued)
Pin No. 10 Equivalent circuit Description Voltage * Waveform Analog B signal B-in 1: Analog B signal input
Pin 6 VCC1
0.7 V[p-p] typ.
10
5 k
Pin 7 VREF
11
Pin 23 GND
Pin 6 VCC1 1 k
R-ch. det.: R-ch. clamping capacitor coupling pin
1 k
11
500
HSS Pin 23 GND
12
1 k Pin 6 V 1 k CC1
G-ch. det.: G-ch. clamping capacitor coupling pin
12
500
HSS Pin 23 GND
13
1 k
Pin 6 VCC1 1 k
B-ch. det.: B-ch. clamping capacitor coupling pin
13
500
HSS Pin 23 GND
SDB00081BEB
11
AN2546FH-A
Terminal Equivalent Circuits (continued)
Pin No. 14 Equivalent circuit Description Voltage * Waveform Analog OSD
0.7 V[p-p] typ.
Pin 6 VCC1
Digital OSD circuit
R-in 2: Character insertion signal input for R-ch., supporting analog and digital OSD
14
5 k
Digital OSD
VDD
Pin7 VREF
15
Pin 23 GND Pin 6 VCC1
G-in 2: Character insertion signal input for G-ch., supporting analog and digital OSD
GND
Analog OSD
0.7 V[p-p] typ.
Digital OSD circuit
15
5 k
Digital OSD
VDD
Pin7 VREF
16
Pin 23 GND
Pin 6 VCC1
GND
Digital OSD circuit
B-in 2: Character insertion signal input for B-ch., supporting analog and digital OSD
Analog OSD
0.7 V[p-p] typ.
16
5 k
Digital OSD
VDD
Pin7 VREF
Pin 23 GND
GND
17
17
15 k 100 k
YS: Character picking up signal input
Pin 23 GND
VDD GND
10 k
18
18
15 k 100 k
BLAK: Black level indication control signal input pin
Pin 23 GND
VDD GND
10 k
12
SDB00081BEB
AN2546FH-A
Terminal Equivalent Circuits (continued)
Pin No. 19 Equivalent circuit
Pin 6 VCC1 100
Description B-out: B signal output pin
Voltage * Waveform
Pin 25 VCC2
19 Pin 23 GND
16 k
20
19 100 k 20 2 k
Pin 6 VCC1
B-ch. AVE det.: B-ch. output DC feedback detection pin
Pin 23 GND
21
Pin 6 VCC1 100
Pin 25 VCC2
G-out: G signal output pin
21 Pin 23 GND
16 k
22
21 100 k 22 2 k
Pin 6 VCC1
G-ch. AVE det.: G-ch. output DC feedback detection pin
Pin 23 GND
23
GND 1: Drive circuits system GND
SDB00081BEB
13
AN2546FH-A
Terminal Equivalent Circuits (continued)
Pin No. 24 100 k 24 2 k 100 k 8 k Pin 23 GND 25 26 VCC2: 7.5 V system power supply R-out: R signal output pin Equivalent circuit Pin 6 VCC1 Description AVE : R,G,B output DC reference voltage pin Voltage * Waveform
Pin 6 VCC1 100
Pin 25 VCC2
26 Pin 23 GND
16 k
27
26 100 k 27 2 k
Pin 6 VCC1
R-ch. AVE det.: R-ch. output DC feedback detection pin
Pin 23 GND
28
200
Pin 25 VCC2
Common out: Voltage output pin for common. Output impedance; Approx. 150 ch.1 ch.1
15 k 28 100 k
Pin 23 GND
14
SDB00081BEB
AN2546FH-A
Terminal Equivalent Circuits (continued)
Pin No. 29 Equivalent circuit Description VCC3: Logic output circuits system power supply 3.0 V typ. Voltage * Waveform
30
Pin 29 VCC3 30 Pin 37 VSS
31
PWM: PWM signal output pin
Output waveform
VCC3
Pin 23 GND Pin 29 VCC3
VD: Vertical synchronous signal output pin
0V
Output waveform
VCC3
31 Pin 37 VSS
32
Pin 23 GND
Pin 29 VCC3
0V
HD: Horizontal synchronous signal output pin
Output waveform
VCC3
32 Pin 37 VSS Pin 23 GND
0V
33
100 100
Pin 44 VCC1
SCP out: Sand castle pulse output pin
Burst time 4.0 V[p-p] typ.
33 350 41.3 k Pin 41 GND
Vertical/Horizontal blanking time
2.0 V[p-p] typ.
34
Pin 29 VCC3 34 Pin 37 VSS
HSS: Composite synchronous signal output pin
Output waveform
VCC3
0V
Pin 23 GND
SDB00081BEB
15
AN2546FH-A
Terminal Equivalent Circuits (continued)
Pin No. 35 Equivalent circuit Description VDB in: Vertical synchronous pulse input pin Voltage * Waveform High or Low
35 15 k 100 k 10 k Pin 23 GND
36
36 15 k 100 k 10 k Pin 23 GND
Ext. pol.: 1H reverse signal input pin
High or Low
37 38
VSS : MOS system GND PRGB: Analog OSD signal input Mode start-up signal input pin Valid only in the analog OSD mode High = Analog OSD start up LDET: Capacitor coupling pin for the horizontal unlock detecting circuit
High or Low
38 15 k 100 k 10 k Pin 23 GND
Pin 44 VCC1
39
200
60 39 60
10 k
12 k
Pin 41 GND
40
VDD: Capacitor connection pin for MOS part power supply 3.0 V typ. GND 2: Pulse system GND
Pin 44 VCC1
41 42
2 k
AFC det.: AFC filter connecting pin Input impedance; 100 k or more 1H
42
1 k
2 k
1 k
Pin 41 GND
16
SDB00081BEB
AN2546FH-A
Terminal Equivalent Circuits (continued)
Pin No. 43 Equivalent circuit Description Voltage * Waveform H fO: VCO oscillation frequency adjusting resistor connection pin
10 k 5 pF 43 2 k
Pin 44 VCC1 10 k
Pin 41 GND
44 VCC1: Pulse system power supply 5.0 V NAVI sync-in: Synchronous signal input pin for the signal of car navigation system Negative polarity input HSS in: Sync. signal input pin Separates a sync. signal from luminance signal (video signal)
45
45 15 k 100 k 10 k Pin 23 GND
VDD
0V Input signal example: Video signal
46
Pin 44 21.7 k 32.5 k VCC1 850 50 k
46
85 Pin 41 GND
47
47 15 k 100 k 10 k Pin 23 GND
SCLK: Serial clock input pin
48
Pin 44 VCC4 48 15 k 100 k 10 k Pin 23 GND
DAT: Serial data input pin
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AN2546FH-A
Terminal Equivalent Circuits (continued)
Pin No. 49 Equivalent circuit Description Voltage * Waveform
5 k 500
Pin 44 VCC1 100 k 50 k
RST: Capacitor coupling pin for power-on reset
49
Pin 41 GND
50
1.5 pF 46 k
Pin 37 VSS
Pin 44 VCC1
Com. DC: DC voltage output pin
DC
50
40 k
36 k Pin 41 GND
51
1.5 pF
Pin 44 VCC1 46 k
DAC-out: DC voltage output pin
DC
51
40 k
36 k Pin 41 GND
Y-in: Luminance signal input pin Input luminance signal (video signal) Input signal example: Video signal
52
50 k 50 2 k 2 k
Pin 58 VCC1
52
53
53
Pin 59 GND
Trap-out: Trap connecting pin Trapping a chrominance signal by connecting external inductor and capacitor. Not necessary in case that an input signal is a component.
18
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AN2546FH-A
Terminal Equivalent Circuits (continued)
Pin No. 54 Equivalent circuit Pin 58 VCC1 54 2 k Description Trap-in: Trap connecting pin The pair with pin 53 Voltage * Waveform
Pin 59 GND 55
1 k
Pin 58 V 1 k CC1
Y-det.: Capacitor coupling pin for luminance signal clamping
55 2 k
Pin 59 GND
56 1 k 2 k 1 k Pin 58 VCC1 ACC det.: ACC capacitor connecting pin, adjusting the amplitude of a burst signal automatically
56 5 k 5 k
1 k
1 k 57
Pin 59 GND Pin 58 VCC1 C-in: Input signal example: Chrominance signal input pin Video signal Input chrominance signal (video signal)
57
50 k
Pin 59 GND 58 VCC1: Power supply 5.0 V typ. Chrominance and luminance signal processing system. GND 3: GND for chrominance and luminance signal processing system
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AN2546FH-A
Terminal Equivalent Circuits (continued)
Pin No. 60 Equivalent circuit Description Voltage * Waveform Kill det.: Killer capacitor coupling pin To prevent degradation of image in a small amplitude of a burst signal, this pin stops a chrominance signal and the mode changes to black and white mode.
Pin 58 VCC1 72 k 60 1.5 k
90 k
61
Pin 59 GND
APC det.: APC capacitor coupling pin Matching the phase of a crystal oscillation to that of burst signal
Pin 58 VCC1
1 k 1 k
31 k 41 k
61 50 k
5 k 5 k 100 k 2 k 1 k 50 k 45 k
2 k Pin 59 GND 62
Pin 58 VCC1 10 k
SCP out: Subcarrier pulse output pin
NTSC 3.58 MHz PAL 4.43 MHz
62
10 k Pin 59 GND
63
Pin 58 VCC1 190 1 k Pin 59 GND
63
VXO1: NTSC crystal oscillator connecting pin Use the capacitor with temperature characteristics (N750) to connect to the crystal oscillator.
20
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AN2546FH-A
Terminal Equivalent Circuits (continued)
Pin No. 64
Pin 58 VCC1 190 1 k Pin 59 GND
Equivalent circuit
Description VXO2: PAL and PAL-M crystal oscillator connecting pin Use the capacitor with temperature characteristics (N750) to connect to the crystal oscillator.
Voltage * Waveform
64
Usage Notes
* The supply voltage applied to pin 6, pin 25, pin 29, pin 44, and pin 58 must be brought up at the same time. * The crystal oscillator used must be evaluated thoroughly, because chrominance signal processing system characteristics change by the crystal oscillator type. * The conversion of the analog RGB signals and the analog OSD signals with synchronous signals is not supported. * Input the analog RGB signals and the analog OSD signals after filtering the pedestal parts of these signals. * Evaluated thoroughly on the application of this device in PAL.
Technical Data
1. Serial interface description 1) I2C bus control mode A serial data is capable of transferring 9-bit unit of 8-bit transfer data and 1-bit answering data using two kinds of signal lines of data and shift clock. When a slave address after setting a start condition matches the address on the IC side, you can receive the data to be transmitted from then. Once the stop condition is set up, the next transmitting data will be ignored until the start condition is set up. There are two kinds of transfer mode: an auto-increment mode which does not transmit subaddress, and data upgrade mode which transmits subaddress + data by 2 bytes. The typical models of communication sequence are shown below: (1) Start condition When the S-data changes from high level to low level at SCLK = high level, a data receiving mode becomes available. (2) Slave address transfer The slave address of the AN2546FH-A is 88h.
Pin 48 S-data 1 Pin 47 SCLK Subaddress transfer Start condition Acknowledge bit 2 3 4 5 6 7 8 9 1 2
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AN2546FH-A
Technical Data (continued)
1. Serial interface description (continued) 1) I2C bus control mode (continued) (3) Subaddress transfer When a data transfer mode bit is 0, all the serial data columns transferred until a stop condition is set is regarded as the data block.
Pin 48 S-data 8 Pin 47 SCLK Slave address transfer Data transfer mode bit "1": Data update mode "0": Auto increment mode Data transfer Acknowledge bit 9 D7 1 D6 2 D5 3 D4 4 D3 5 D2 6 D1 7 D0 8 9 1 2
(4) Data transfer
Pin 48 S-data 8 Pin 47 SCLK Acknowledge bit At auto increment mode: Data transfer At data update mode: Stop condition 9 D7 1 D6 2 D5 3 D4 4 D3 5 D2 6 D1 7 D0 8 9 1 2
(5) Stop condition When S-data changes from low level to high level at SCLK = high level, data reception is halted. (6) Pulse timing Timing chart expanded diagram
Pin 48 S-data tBUF tLOW Pin 47 SCLK tHDDAT tf
tSUSTO tHDSTA tr tHIGH tSUDAT
Parameter SCLK clock frequency Bus free-time for stop condition and start condition Hold time start condition SCLK clock low-state hold time SCLK clock high-state hold time Data hold time Data setup time S-data and SCLK signal rise time S-data and SCLK signal fall time Stop condition setup time 22
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Symbol tSCL tBUF tHDSTA tLOW tHIGH tHDDAT tSUDAT tr tf tSUSTO
Min 0 1.3 0.6 1.3 0.6 0 100 0.6
Typ
Max 400 300 300
Unit kHz s s s s s ns ns ns s
AN2546FH-A
Technical Data (continued)
1. Serial interface description (continued) 2) Mode setting channel bits table ch. Sub- Initial value address (HEX) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 80 80 80 80 40 80 80 80 80 C0 80 80 80 80 80 80 03 00 80 80 80 7F 80 80 EXTTEST DHTS EXCHFI DFVD MACRON HOSEI DFSC PWMT4 DPALM KOTEI DCLP DBOSC HGA D7 D6 D5 D4 D3 D2 D1 D0
Common amplitude Luminance gain Color gain Hue Black limiter Brightness Aperture R-ch. sub-brightness B-ch. sub-brightness White peak limiter Gamma 1 Gamma 2 Contrast R-ch. sub-contrast B-ch. sub-contrast VCO free-run *1 DPALN DSECAM DVMODE DUV DCINT PLL stop position adjustment BLAK PWM duty POLSW DMOSD
*2
Vertical position adjustment Burst cleaning pulse position adjustment DSC DCPS DQPAL
Horizontal position adjustment
PWM frequency adjustment
Common DC
DC output adjustment
Note) *1: VCO free-run adjustment; ch.23 = 02h or more, EXTTEST = High *2: 00h, 01h are prohibition of use because of test mode.
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AN2546FH-A
Technical Data (continued)
1. Serial interface description (continued) 2) Mode setting channel bits table (continued) (1) ch.5: Black limiter adjustment Subaddress 05 D7 HGA 0 1 D6 D5 D4 D3 D2 D1 D0
Output gain down mode Gain mode
(2) ch.7: Aperture adjustment Subaddress 07 D7 DCLP 0 1 D6 D5 D4 D3 D2 D1 D0
VD free-run: NTSC = 265H, PAL = 315H VD free-run : NTSC = 263H, PAL = 313H
(3) ch.10: White peak limiter adjustment Subaddress 0A D7 DCLP 0 1 D6 D5 D4 D3 D2 D1 D0
NAVI sync. mode (Pin 45) Video sync. mode (Pin 46)
(4) ch.17: Mode setup 1 Subaddress 11 Mode DFVD DFSC DPALM DPALN DSECAM DVMODE DUV DCINT 0 1 0 1 D7 DFVD D6 DFSC D5 DPALM D4 DPALN D3 D2 D1 DUV D0 DCINT
DSECAM DVMODE * at NTSC selection
Function VD cycle: 60 Hz VD cycle: 50 Hz Subcarrier: 3.58 MHz Subcarrier: 4.43 MHz
DFVD/DFSC/DPALM/DPALN/DSECAM = Low DVMODE = High * at PAL selection DFVD/DFSC = High DPALM/DPALN/DSECAM/DVMODE = Low * at PALM selection DPALM/DFVD = High DPALN/DSECAM/DVMODE = Low * at PALN selection DPALN = High DPALM/DSECAM/DVMODE/DFVD = Low
High = PALM mode on High = PALN mode on High = SECAM mode on High = Burst swing off 0 1 0 1 Chrominance input Color difference signal input RGB signal input Video signal input
(5) ch.18: PLL stop position and vertical sync. output position adjustment Sub12 D7 0 1 D6 D5 D4 D3 D2 D1 D0 address MACRON
PLL stop position adjustment AFC normal operation Copy guard signal correspondence
Vertical position adjustment
24
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AN2546FH-A
Technical Data (continued)
1. Serial interface description (continued) 2) Mode setting channel bits table (continued) (5) ch.18: PLL stop position and vertical sync. position adjustment (continued)
Composite sync. signal odd number field Pin 35 input
Pin 31 output odd number field FIXHD = "0" Pin 31 output odd number field FIXHD = "1" 3
8H 2H to 9H (D0 to D2)
Composite sync. signal even number field Pin 31 output EXCHF = "1" FIXHD = "0" Pin 31 output EXCHF = "1" FIXHD = "1" Pin 31 output EXCHF = "0" FIXHD = "0" 8H 1.5H to 8.5H (D0 to D2) 3
8H 2.5H to 9.5H (D0 to D2) The above timing chart indicates (D2,D1,D0) = "101". For (D2,D1,D0) = "000", the pin 32 output width is 9H.
Pin31 output EXCHF = "0" FIXHD = "1"
3
The pin 31 timing is synchronous with the pin 35 input timing. The above timing chart is just for reference

0-line Composite sync. signal odd number field Pin 35 input 6H to 9H (D3 to D4) Odd number field Composite sync. signal even number field 5.5H to 8.5H (D3 to D4) EXCHF = "1" Horizontal PLL off 6.5H to 9.5H (D3 to D4) EXCHF = "0" Horizontal PLL off Horizontal PLL on The above timing chart indicates (D4,D3) = "01". PLL stop line number: 254-line (NTSC) 302-line (PAL)
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2
3
Horizontal PLL off
Horizontal PLL on
Horizontal PLL on
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AN2546FH-A
Technical Data (continued)
1. Serial interface description (continued) 2) Mode setting channel bits table (continued) (6) ch.19: Horizontal sync. output position adjustment Subaddress 13 0 1
Composite sync. signal input (video signal) Pin 34 Composite sync. signal output 27fy Pin 32 Horizontal sync. signal output (D4,D3,D2,D1,D0) = (00000) Pin 32 Horizontal sync. signal output (D4,D3,D2,D1,D0) = (11111) Pin 32 Horizontal sync. signal output (D5) = "1" 31fy 27fy 1fy = 1 (NTSC/PAL) 347fh fh: Horizontal sync. frequency Delay time (Approximately 400 ns) 18fy
D7 HOSEI
D6 PWMT4
D5 KOTEI 0 1
D4
D3
D2
D1
D0
Sync. output variable mode Sync. output fixation mode
PWM frequency adjustment
VCO automatic adjustment off VCO automatic adjustment on
Sync. signal separation delay time (Approximately 1 s)
The delay time of pin 34 output to video signal is likely to vary according to an external constant connected to pin 46. For an external constant, the characteristics in weak electric field must be evaluated adequately. Though the horizontal sync. signal output adjustment range is designed by referring to the center of pin 34 output pulse, there would be some error according to VCO free-run frequency. (7) ch.20: PWM frequency and burst cleaning pulse width adjustment Subaddress 14 D7 D6 D5 D4 D3 BLAK 0 1 D2 D1 D0 PWM frequency adjustment Burst cleaning pulse adjustment Black level variable mode Black level fixation mode
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Technical Data (continued)
1. Serial interface description (continued) 2) Mode setting channel bits table (continued) (8) ch.22: Mode setup 2 Subaddress 16 Mode EXTTEST DHTS EXCHFI POLSW DMOSD DSC DCPS DQPAL 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D7 EXTTEST D6 DHTS D5 EXCHFI D4 POLSW D3 DMOSD D2 DSC D1 DCPS D0 DQPAL
Function Normal mode Test mode 1H reverse stop 1H reverse Odd number field: Advance phase Even number field: Advance phase Internal POL 1H reverse mode External POL 1H reverse mode Analog OSD signal input Digital OSD signal input Subcarrier output stop Subcarrier output Component input mode Composite input mode STD PAL mode Quasi PAL mode
2. Recommended Operating Conditions Parameter Composite video input signal Y-input signal voltage C-input signal voltage MOS input signal low-level voltage Symbol YIN YIN CIN VMOSL Condition Sync. chip - White Pedestal - White Burst signal amplitude Min 0.9 0.6 200 0 2.1 Pedestal - Sync. chip Pedestal - White 0.2 0.6 Typ 1.0 0.7 300 0.3 0.7 Max 1.1 0.8 Unit V[p-p] V[p-p]
400 mV[p-p] 0.9 *1 0.4 0.8 V V V[p-p] V[p-p]
MOS input signal high-level voltage VMOSH Sync. signal input Analog RGB signal input HSYNC RGBIN
Note) *1: Set it lower than VCC1 (Pin 6 voltage).
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AN2546FH-A
Technical Data (continued)
3. Power dissipation of package QFP064-P-1010 PD T a
1.600 1.576 1.400 Mounted on standard board (glass epoxy: 75 x 75 x t0.8 mm3) Rth(j-a) = 79.3C/W
1.200
Power dissipation PD (W)
1.000 0.814 0.800
0.600 Independent IC without a heat sink Rth(j-a) = 153.5C/W
0.400
0.200
0.000 0 25 50 75 100 125 150
Ambient temperature Ta (C)
New Package Dimensions (Unit: mm)
* QFP064-P-1010A (Lead-free package)
12.000.20 10.000.20 48 49 33 32
(1.25) 10.000.20 12.000.20 0.100.10 1.950.20
64 1 0.50
17 16 0.180.05
(1.25)
0.10 M
0.10 Seating plane (1.00)
0.150.05
0 to 10 0.500.20
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Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this material. (4) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (5) The products and product specifications described in this material are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.
2002 JUL
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